IO_ICU1            51 arch/i386/include/i8259.h #define SET_ICUS()	(outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
IO_ICU1            93 arch/i386/include/i8259.h 	outb	%al,$IO_ICU1
IO_ICU1           104 arch/i386/include/i8259.h 	outb	%al,$IO_ICU1
IO_ICU1           114 arch/i386/include/i8259.h 	outb	%al,$IO_ICU1
IO_ICU1           188 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1, 0x11);		/* reset; program device, four bytes */
IO_ICU1           189 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1+1, ICU_OFFSET);	/* starting at this vector index */
IO_ICU1           190 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
IO_ICU1           192 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1+1, 2 | 1);		/* auto EOI, 8086 mode */
IO_ICU1           194 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1+1, 1);		/* 8086 mode */
IO_ICU1           196 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1+1, 0xff);		/* leave interrupts masked */
IO_ICU1           197 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1, 0x68);		/* special mask mode (if available) */
IO_ICU1           198 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1, 0x0a);		/* Read IRR by default. */
IO_ICU1           200 arch/i386/isa/isa_machdep.c 	outb(IO_ICU1, 0xc0 | (3 - 1));	/* pri order 3-7, 0-2 (com2 first) */