HCCR 205 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); HCCR 239 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); HCCR 509 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_RESET); HCCR 536 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_STEP); HCCR 551 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_2X00_DISABLE_PARITY_PAUSE); HCCR 555 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); /* release paused processor */ HCCR 3526 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); HCCR 3544 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); HCCR 3581 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); HCCR 3626 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); HCCR 4755 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); HCCR 5282 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT); HCCR 5346 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT); HCCR 6420 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); HCCR 6423 dev/ic/isp.c if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { HCCR 6427 dev/ic/isp.c if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { HCCR 6508 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); HCCR 6511 dev/ic/isp.c if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { HCCR 6515 dev/ic/isp.c if ((ISP_READ(isp, HCCR) & HCCR_PAUSE) == 0) { HCCR 6520 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); HCCR 6523 dev/ic/isp.c if ((ISP_READ(isp, HCCR) & HCCR_PAUSE) == 0) { HCCR 6564 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); HCCR 6567 dev/ic/isp.c if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { HCCR 6571 dev/ic/isp.c if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { HCCR 1235 dev/pci/isp_pci.c isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);