CZTTY_CHAN_WRITE  431 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE);
CZTTY_CHAN_WRITE  432 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS);
CZTTY_CHAN_WRITE  433 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0);
CZTTY_CHAN_WRITE  434 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11);
CZTTY_CHAN_WRITE  435 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13);
CZTTY_CHAN_WRITE  436 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED);
CZTTY_CHAN_WRITE  437 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE);
CZTTY_CHAN_WRITE  438 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP);
CZTTY_CHAN_WRITE  439 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0);
CZTTY_CHAN_WRITE  440 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS);
CZTTY_CHAN_WRITE  441 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0);
CZTTY_CHAN_WRITE  931 dev/pci/cz.c   	CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE);
CZTTY_CHAN_WRITE  997 dev/pci/cz.c   		CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE);
CZTTY_CHAN_WRITE 1246 dev/pci/cz.c   	CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control);
CZTTY_CHAN_WRITE 1286 dev/pci/cz.c   	CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control);
CZTTY_CHAN_WRITE 1443 dev/pci/cz.c   	CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud);
CZTTY_CHAN_WRITE 1444 dev/pci/cz.c   	CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l);
CZTTY_CHAN_WRITE 1445 dev/pci/cz.c   	CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity);
CZTTY_CHAN_WRITE 1446 dev/pci/cz.c   	CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow);
CZTTY_CHAN_WRITE 1447 dev/pci/cz.c   	CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control);